Facebook is the End Client UVM... driver monitor scoreboard agent development System Veri...

ASIC IP Verification UVM Development AHB/AXI PERL Python

Analog Circuit Design Physical design STA Tcl Spectre

C C++ System Verilog Xcelium UVM

ASIC Verilog System Verilog UVM Perl

Autosar Embedded Software Embedded Testing Perl python

Verilog system Verilog UVM VMM

Formality CDC Design Strong analytical System Verilog

VERIFICATION ENGINEER HDL HVL VERILOG SYSTEM VERILOG

C++ OOP System Verilog UVM OVM

C/c++ Json Eda Simulation Python System Verilog

Perl Python Vhdl Verilog System-verilog

Perl Tcl C Shell Pytho Systemverilog

C C++ Assembler Amba Python

C-shell Scripting Verilog-hdl System Verilog Python C