GPIO UART SPI SW JTAG

C++ OOP System Verilog UVM OVM

ASIC design Perl Python Verilog EDA

SystemVerilog Verilog RTL Design Synopsys Cadence

VERIFICATION ENGINEER HDL HVL VERILOG SYSTEM VERILOG

Verizon T-Mobile Comcast

Hardware Validation Verilog LabViEW Python C++

VHDL Verilog Cadence OrCad Xilinx Vivado Altera

SOC Verification Verilog UVM SV

Perl Python Tcl Verilog NDM

HardwareDesignDeveloper Verilog SystemVerilog VHDL Scripting

Formality CDC Design Strong analytical System Verilog

ASIC CAD tools Developing Verilog RTL Functional Behavioral Models

Xilinx FPGAs Verilog

Network security Cybersecurity C C++ Verilog