Mask Layout Design Engineer

Job Title: Hardware Engineering and R&D - Hardware Design Engineer 1
Location: Morrisville, NC (Remote)
Duration: 6 Months on W2

Overview:
We are looking for an experienced Mask Layout Design Engineer who is innovative and has a passion for IC Layout design of high-speed CMOS Interface D2D and SERDES for next generation Consumer & Cloud Computing Devices.

The ideal candidate is a self-starter, highly motivated engineer with excellent technical & interpersonal skills, used to working independently or as a key member of a fast-moving design team.

Responsibilities:
The primary responsibility of this position entails executing IC layout of cutting edge, high-performance, high-speed, low power CMOS Interface D2D and SERDES integrated circuits in foundry CMOS process nodes in 2nm and 3nm following industry best practices.

You will be responsible for all or parts of the following areas:
• Using Cadence Virtuoso design tool and flow
• Will be working on highly analog IPs like analog PLL, DLL, Client, RX, TX, OTAs, LDO, Clock Distribution, Bandgap and Bias
• Layout Design review presentations.
• Layout floor-planning and supervision.
• Physical LVS, DRC, DFM

Candidate Requirements
• Years of Experience Required: 0-2 overall years of experience in the field.
• Degrees or certifications required: NO degree is required to be eligible for this role.
• MSFT experience is nice but not required.
• Disqualifiers: Candidates without hands on experience will not be eligible for the role.
• Best vs. Average: The ideal resume would contain below qualifications.
• Performance Indicators: Performance will be assessed based on productivity – assignment completion, timely delivery.

Qualifications:
• You should have min 1 years of experience in high performance analog layout in advanced FINFET CMOS process, 2nm and 3nm preferred, BS degree a plus
• Detailed knowledge of EDA tools for Cadence, Mentor and Synopsys.
• Having experience with layout of high-performance analog blocks such as VCOs, chargepump, phase interpolators, clock distribution, bandgap, OTAs, PLLs, ADCs, LDOs, RX, TX, references, etc. is desired.
• Knowledge of analog design and layout guidelines and high-speed IO.
• Experience with floor planning, block level routing and large macro level assembly.
• Knowledge of high-performance analog layout techniques such as common centroid layout, matching, symmetrical layout, signal shielding, use of dummy devices, thermal aware layout with consideration for electro migration, IR, ESD and other analog specific guidelines.
• Confirmed experience with analog layout for silicon chips in mass production.
• Worked with sub-micron design in foundry CMOS nodes 2nm, 3nm and 5nm FINFET.
• Requires self-starter with the ability to define and adhere to a schedule

Hard Skills Assessments
• Expected Dates that Hard Skills Assessments will be scheduled: ASAP.
• Hard Skills Assessment Process: The assessment process will include HSA With the sponsor.
• Required Candidate Preparation: N/A

Top 3 Hard Skills Required + Years of Experience
1. Minimum 2 years experience with high performance analog layout in advanced FINFET CMOS process, 2nm and 3nm preferred, BS degree a plus
2. Minimum 2 years experience with Detailed knowledge of EDA tools for Cadence, Mentor and Synopsys.
3. Minimum 2 years experience with layout of high-performance analog blocks such as VCOs, chargepump, phase interpolators, clock distribution, bandgap, OTAs, PLLs, ADCs, LDOs, RX, TX, references, etc. is desired.