React JavaScript TypeScript Jest RTL

C++ OOP System Verilog UVM OVM

ASIC design Perl Python Verilog EDA

SystemVerilog Verilog RTL Design Synopsys Cadence

FPGA RTL AMD Xilinx Altera Quartus

LPDDR DDR IPs. RTL FW circuit

CDC ASIC AXI AHB APB

C++ SystemVerilog RTL Python SoCs

ASIC CAD tools Developing Verilog RTL Functional Behavioral Models

RTL TypeScript React.js JavaScript

RTL Jest testCafe React.js

Analog Semiconductors Circuit Design Logic Gates Mixed-Signal IC Design Product Introduction

CSS HTML JavaScript MongoDB RTL Design

Autosar Embedded Software Embedded Testing Perl python

FPGA design Xilinx/Altera RTL synthesis Verilog VHDL