WBS SAP FICO EVM SAP GL AP

C++ OOP System Verilog UVM OVM

ASIC design Perl Python Verilog EDA

SystemVerilog Verilog RTL Design Synopsys Cadence

SAP BRIM SAP CI OTC (BRIM) RTR (Finance) TR (Treasure)

Agile

requirement document (SRS) Requirement Traceability Matri... and Functional Specification D...

FPGA RTL AMD Xilinx Altera Quartus

GCP AWS Azure Docker RESTful web services

Embedded C C++ RTOS QNX Linux

Ruby on Rails s Javascript

Linux JavaScript HTML5 CSS3 Angular

Python Simulink C C++ Matlab

SAP S/4HANA SAP R2R

Mainframes COBOL PL/1 CICS JCL