ASIC design Perl Python Verilog EDA

SystemVerilog Verilog RTL Design Synopsys Cadence

SAP BRIM SAP CI OTC (BRIM) RTR (Finance) TR (Treasure)

Agile

requirement document (SRS) Requirement Traceability Matri... and Functional Specification D...

FPGA RTL AMD Xilinx Altera Quartus

AWS platform bedrock sage maker GTE model

Embedded C C++ RTOS QNX Linux

T-SQL SSMS SQL PowerShell MySQL

Oracle ERP

Oracle PL/SQL Forms Reports Workflows

Oracle HCM BI publisher Workflow ALERT BIP

scripting TTS Java Python JavaScript

SSRS Tableau Alteryx AWS Docker

XML SQL/PLSQL Shell Scripts Workflows