Agile Release Train (ART) Scaled Agile Framework (SAFe) Release Train Engineer (RTE)

C++ OOP System Verilog UVM OVM

ASIC design Perl Python Verilog EDA

SystemVerilog Verilog RTL Design Synopsys Cadence

SAP BRIM SAP CI OTC (BRIM) RTR (Finance) TR (Treasure)

Agile

requirement document (SRS) Requirement Traceability Matri... and Functional Specification D...

FPGA RTL AMD Xilinx Altera Quartus

Embedded C C++ RTOS QNX Linux

Python Simulink C C++ Matlab

Mainframes COBOL PL/1 CICS JCL

Waterfall Scrum Agile MATLAB SIMULINK

C-suite SharePoint Teams PowerPoint Word

CSM CSPO SAFe RTE PMI-ACP ART

Release Release Train Engineer RTE iOS Android