Description

Key Responsibilities:

Develop and implement ASIC emulation plans for SoC designs.
Collaborate with cross-functional teams to validate hardware and software integration.
Debug and resolve issues in the emulation environment.
Optimize emulation performance and coverage.
Provide feedback to design and verification teams to improve design quality.


Qualifications:

Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field.
Experience with FPGA-based emulation platforms (e.g., Synopsys, Cadence)
Strong knowledge of SoC architecture, RTL design, and verification.
Proficiency in Verilog/System Verilog and scripting languages.

Education

Any Graduate