JOB Description:
As a member of the IP team, the candidate would be responsible for setup and execution of IP level synthesis runs, debug and analysis of results on a weekly basis. This position would require the individual to draw upon proven industry design experiences to ensure successful program execution.
KEY RESPONSIBILITIES:
- Define synthesis recipe with block leads
- Analyze results and debug any failures with design leads
- Act as a liaison between IP and SOC design teams for synthesis and physical layout issues
- Signoff IP quality for delivery into SOC
- Work with Central Engineering teams on new flow adoption and execution
- Effectively communicate results with multi-disciplined teams
- Gather, attend and present into technical status meetings on a weekly basis
PREFERRED EXPERIENCE:
- Proven RTL design experience on large ASIC development projects
- Strong background working with industry standard synthesis tools, flows and back-end timing closure(e.g. Formality, CDC & Linting tools, Design Compiler/FX etc)
- Strong background in Verilog, System Verilog and/or scripting
- Strong analytical skills and attention to detail
- Excellent written and communication skills
- Experience with display/display related technologies is an asset
- Understanding of the IP integration and interactions within an SOC is an asset
- Must be a self-starter and able to independently drive tasks to completion
- Demonstrates the ability to debug issues and quickly identify viable solutions
- Team player with proven leadership skills