CPU RTL Design Engineer

About the job
Responsibilities

Design and develop IP’s, Subsystems, SOC integration.
Develop CPU subsystem front-end designs, emphasizing on microarchitecture and RTL design for the next generation CPU.
Capable of designing fully configurable design features, assessments, refinements of RTL design targeted to performance, power and timing goals.
Microarchitecture development and specification - From early high-level architectural exploration, through micro architectural research and arriving at detailed specification.
Deliver designs meeting Power, Performance and Area (PPA) goals with production quality
Required to handle re-designing, porting designs from older designs with adding new features, changes to existing design for meeting newer technology advancements.
Functional verification support - help the design verification team execute the functional verification strategy.
Work with multi-functional design and verification teams, coordination with team members located in different geographic locations and time zones.
Handle clocking, reset architecture and data flows. Has knowledge of SoC bring-up, bus protocol, register and address map Verification. 
Design delivery - work with multi-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability, and power. 
Gain customer satisfaction by taking responsibilities, adopting to new design concepts, leading the team.
 

Preferred Experience

Excellent track record in designing IP’s, Subsystems involving CPUs, bus interconnects.
Working experience on Fetch Unit, MMU/IO-MMU, Load-Store, RISCV-Privilege Architecture, Advance Interrupt Architecture.
Worked with IP’s or Subsystem involving CPUs like RISC-V, ARM or x86 is a big plus.
Knowledge of computer architecture, CPU designs like RISC-V, ARM & x86 ISA.
Well versed with understanding the systems using CPUs, security, safety.
Knowledge of In-Order, Out-of-Order execution, cache coherency, memory systems.
Understanding of Instruction fetch, Load & Store, FPU, ALU
Understanding of Debug and Trace infrastructure.
Design concepts configurability, scalability, automation. 
Knowledge of AMBA bus protocols, DMA concepts.
Hands on experience with RTL coding using SV, Verilog, scripting language (Perl, Python, shell, TCL)
Good analytical and problem-solving skills.
Mentor junior engineers on the team
 

Qualifications

Bachelor’s/MS engineering in Electronics, Electrical, Computer Science or related fields. 
6 to 15+ years of experience in ASIC design
Experienced with EDA tools, RTL coding, low power techniques, Lint, CDC and timing.
Knowledge of logic design principles along with timing, performance and power implications
Ability to collaborate effectively with cross-functional teams
Excellent problem-solving and analytical skills
Strong attention to detail and ability to work in a fast-paced environment.