Design Engineer

Minimum qualifications

10+ Years of experience in backend implementation such as synthesis, timing closure, power analysis etc.

Experience with power analysis and tools like PTPX (must have).

Experience with RTL Synthesis and design optimization for Power, Performance, Area.

Experience with EDA tools and scripting languages (Python, TCL) used to build tools and flows for complex environments.

Experience with communicating across functional internal teams and vendors.

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.

Responsibilities:

Run Logic/Physical Synthesis and generate optimized Gate Level Netlist for Timing, Area, Power. Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them.

Perform Power Estimation at RTL and Gate Level and identify power reduction opportunities.

Perform RTL Lint and work with the Designers to create waivers.

Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top-level including SOC. Analyze the inter-block timing and come up with IO budgets for the various partition blocks.

Developing Automation scripts and Methodology for all FE-tools including (Lint, CDC, RDC, Synthesis, STA, Power).

Work closely with the Design Engineers, DV Engineers, Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback.