Digital Design Engineer

JOB DESCRIPTION:

Qualifications

· Bachelor’s or Master’s degree in electrical or Electronics Engineering

· At least 6+ years of experience in designing digital logic using system Verilog

· Experience in integrating mixed-signal IP with digital logic

· Experience working multi-functionally with architecture, design, and verification teams to specify, design, and debug designs

· Experience in block level logic synthesis and STA

· Experience in working with physical design team to close timing

· Good collaboration skills with strong written and verbal communication skills

· Basic scripting skills

Responsibilities

· Write microarchitecture and implement block level logic design using System Verilog

· Integrate digital design with mixed signal IP for block level simulation

· Coding high-quality RTL, with embedded assertions and cover points

· Clean up design with LINT/CDC/RDC

· Work with Verification team prepare test plan, design debug and code coverage improvements

· Develop and analyze functional coverage

· Debug any behavioral RTL issue in Mixed-Signal IP

· Work closely with physical design team to close design timing issues
RTL coding, synthesis and Digital Design architecture fundamentals
SystemVerilog (Priority: 1)
Synthesis tools (Priority: 1)
Python/TCL (Priority: 3)
Primetime (Priority: 2)
Synopsys DC-Compiler (Priority: 2)

Experience working multi-functionally with architecture, design, and verification teams to specify, design, and debug design