Description

Top 5 Required Skills

1. Must possess 6-8 years of hands-on experience in P&R from Netlist to GDS including timing closure and Physical verification.

2. Power user of industry standard Physical Design & Verifaction tools.Innovus,FirstEncounter,ICC, etc.

3. Hands-on experience in floorplanning, clock tree synthesis, timing closure, signal integrity, IR drop analysis, ECO implementation, and physical design verification

4. Experience in Technology nodes: 28nm,14nm

5. Solid understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level.

 

Technologies: What does this temp must know to perform the required job duties

• Work with FE team to understand chip architecture and drive physical aspects early in design cycle.

• Work with physical design team, drive methodologies and "best known methods" to streamline physical design work, produce guidelines and checklists, drive execution, and track progress.

• Resolve design and flow issues related to physical design, identify potential solutions and drive execution.

 

Required Education

• Bachelor’s degree *Preferred but hand on work experience is acceptable.

 

Required Years of Experience:

•8-1 2 years of experience

Education

Any Graduate