Hardware Engineer opportunity

Job Description Below Note: This role is similar to Physical Design Verification role. Develop and support block-level and full chip automated PDV flows and scripts. As a member of our physical design team, you will perform various types of physical verification checks (such as LVS, DRC, design-for-manufacturing & design-for-yield, and lithography) at the chip and block level. Contribute to top-level tasks such as padring, bump placement, RDL design and contribute towards top-level floorplan and integration and work with the packaging team Execute SOC GDSII integration, seal ring addition and generate tapeout collateral to be sent to the foundry. Experience with Innovus is required and Pegasus (from Cadence) would be preferred but not required. Skills: Chip Planning Seal Ring Chip Level Physical Verification Design-for-Yield Lithography (LPC checks) Electrical Rule Checks (ERC) Antenna Physical verification tool – Caliber and IC validator