Physical Design Engineer

Responsibilities:

Floorplanning: Collaborate with the design team to develop floorplans that meet performance, area, and power requirements for IC designs
Placement and Routing: Perform block-level and chip-level placement and routing to optimize performance, minimize area, and ensure signal integrity
Clock Tree Synthesis (CTS): Design and optimize clock distribution networks to achieve low skew, high frequency, and low power consumption
Power Distribution Network (PDN): Design and optimize power grids to deliver clean and stable power to IC components while minimizing IR drop and voltage noise
Physical Verification: Perform physical verification checks such as DRC (Design Rule Check) and LVS (Layout vs. Schematic) to ensure layout compliance with design rules and functionality
Timing Closure: Collaborate with timing closure teams to achieve timing targets, resolve timing violations, and perform timing optimization techniques such as placement optimization and buffer insertion
Design for Manufacturability (DFM): Implement DFM techniques to improve manufacturability, yield, and reliability of IC designs
Collaboration: Work closely with design teams, CAD (Computer-Aided Design) engineers, and other cross-functional teams to address design challenges and achieve design goals
Documentation: Maintain documentation related to physical design methodologies, implementation details, and design specifications

Qualifications:

Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field
Experience: 4-8 years of experience in physical design of complex ICs, including experience with leading-edge technologies and tools
Tools and Technologies: Proficiency in using industry-standard physical design tools such as Cadence Innovus, Synopsys ICC, Mentor Calibre, etc., and familiarity with scripting languages like Tcl, Perl, or Python for design automation
Physical Design Flow: Solid understanding of the entire physical design flow, including floorplanning, placement, routing, CTS, PDN, and physical verification
Timing Closure Techniques: Experience with timing closure techniques such as static timing analysis (STA), clock skew optimization, and hold time fixing
DFM and Yield Enhancement: Knowledge of DFM techniques, yield enhancement strategies, and methodologies to improve IC manufacturability and yield
Problem-Solving Skills: Strong analytical and problem-solving skills to address complex physical design challenges, optimize designs, and meet performance targets
Communication and Teamwork: Excellent communication and teamwork skills to collaborate effectively with cross-functional teams, present design solutions, and drive design success