Senior FPGA Engineer

Job Description:

• 7+ years of FPGA design principles.
• 5+ years working with Xilinx/Altera FPGA.
• Must have done RTL synthesis, constraints design, timing closure.
• Must have experience with design and test bench development to verify the RTL design using Verilog, VHDL or SV/UVM.
• Must have DO-254 and Aerospace background with SV/UVM skills.
• Must be able to develop Communications and fault logging CPLD/FPGA design.
• Must have experience in developing PHAC, HDP, Requirements capture, design documentation.
• Must have hands-on experience with Cadence or Client tool, Microsemi Libero or Xilinx Vivado tool.
• Familiar with SCRUM/Sprint JIRA process.