Analog / Mixed Signal Engineer

Description

• In this role, you will develop an analog, mixed-signal framework for modeling battery management module functionality and performance. Primary subsystems include analog and power management IP: A/D converters, gate drivers + power FETs fault detection circuitry, and command/control state machines. You will model analog and digital control loops involved in current and voltage regulation with attention to stability and transient response.
• You will drive learnings from factory data and hardware builds back into the modeling environment to improve predictive accuracy. With behavioral and statistical simulation techniques, you will assess hardware compliance to engineering specifications, thus quantifying design margin and highlighting implementation risk. Using modeling tools and simulation flows, you will support root cause failure analysis as needed.
• You will provide technical leadership across Battery Hardware Engineering in simulation methodologies, tools, and workflows.

Key qualifications

• Experience with complex analog and digital simulation environments, behavioral modeling techniques, and hardware description languages: Verilog-AMS, Verilog, System-Verilog.
• Experience in AMS verification: test case definition, execution management, coverage analysis, and identifying failure possibilities through directed and random testing.
• Familiar with IC design and simulation tools such as Virtuoso ADE, ADEXL, Ocean, Spectre, Incisive/Xcelium
• Experience with scripting/programming languages such as Python, Matlab, TCL, Skill for analyzing data and automating repetitive tasks.
• Familiarity with statistical analysis and product engineering limit setting practices based on characterization data and Cpk; Monte-Carlo simulation techniques.
• Good written and verbal communication skills. Polished presentation skills. Ability to collaborate well with cross-functional teams and external vendors.

Education and experience

• BS in electrical engineering or related technical discipline with 8+ years of chip top-level management and analog/mixed signal design or verification experience.
• MS/PhD preferred.