Description

Job Description


Design Verification Engineer
Remote
Full Time


Job Description

  • Facebook is the End Client
  • UVM/ System Verilog - sequences, driver, monitor, scoreboard, agent development
  • System Verilog OVM/UVM
  • Python
  • Perl
  • Shell scripting assertions (SVA)
  • Digital ASICs Design

SKILL MATRIX

  • System Verilog OVM/UVM
  • Python
  • Perl
  • Shell scripting assertions (SVA)
  • Digital ASICs Design
  • Can work in PST TimeZone - Yes / No

Key Skills
Education

Any Graduate

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