Design Verification Engineer

Top 5 Required Skills

1. 5 + Years experience in ASIC design, verification, or related work experience

2. Strong UVM, System Verilog Skills

3. 5 + years in experience with scripting tools and programming languages

4. Quick understanding of Specs and Standards and developing relevant and thorough test plans

5. Candidates should be comfortable checking builds, navigating test benches, analyzing coverage, and adding or enabling extra debug. 

Technologies:

ASIC IP Verification

UVM Development

Bus protocols – AHB/AXI

PERL

Python 

Required Education:

Bachelor's degree in Science, Engineering, or related field.

Required Years of Experience: 8-12 years of experience

Physical Requirements (Lifting, outdoor work, travel): 

• Frequently transports between offices, buildings, and campuses up to ½ mile.

• Frequently transports and installs equipment up to 5 lbs.

• Performs required tasks at various heights (e.g., standing or sitting).

• Monitors and utilizes computers and test equipment for more than 6 hours a day.

• Continuous communication which includes the comprehension of information with colleagues, customers, and vendors both in person and remotely.

Key Words:

Design Verification

UVM

System Verilog

PERL/Python

AHB/AXI

Job Description:

As a member of this team, your responsibilities will include:

* Work closely with design, architects and verification leads to develop the IP verification strategy and testplan.

* Create verification environment using UVM/System Verilog.

* Resolve architecture, design or verification problems by applying sound ASIC engineering practices.

* Write tests and regressions to identify any bugs.

* Develop functional coverage model, assertion checkers and scoreboards.

* Interpret the results of performance checks and identify issues.

* Communicate directly with lead on any significant deviations from the Plan of Record for assigned block in a timely manner.

* Perform RTL code coverage, assertion coverage, functional coverage analysis and gate level simulations

* Identify opportunities for productivity improvements. Drive and adopt new verification methodologies and flows for efficiency improvements.