Design Verification Engineer

Job Description:

Good understanding of ASIC verification concepts and techniques. Very good knowledge of Verilog/System Verilog and UVM.

Experience and knowledge in Verification of IP’s related to different applications. Good Knowledge in Power aware verification and Gate level verification is preferable. Should be able to understand the Full-chip Verification requirements as well and good knowledge in industry standard protocols.

• Will be part of a team that handles Verification for complex IP’s and close the Verification to the challenging milestones.
• IP Verification: VR creation as per the chip requirements and UVM/OVM Test benches creation
• Support in building verification infrastructure at the chip level as per the requirements
• Capable of handling multiple areas of IP Verification: RTL, Power Aware and Gate Level Verification
• Working with the team and functional leads; Some interaction with cross functional groups;

The candidate should have good understanding on ASIC/SOC design and verification flow and should have:

• Have experience of digital IP verification with SV/UVM/Formal Verification or new methodology of the industry.

• Good experiences with simulation model creation and testbench build (better with UVM)

• Good logical thinking and expression. Can describe a technical issue/topic to audience not familiar with it.

• Good cooperation cross teams.

• It’s a plus if have one or more of the following experience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, PCIe protocol.

• It’s a plus if have f/w writing and debug experience or experience to co-work with f/w team for f/w sequence define in embedded design.

• It’s a plus to be good at some script language, such as Perl, python. Or some database experience (for IP technical info maintain).

• It’s also a plus if have over 2 years’ experience focusing on SV assertion/coverage/formal verification.