Description

About the job
Position: Design verification Engineer with Python Coding

Location: Sunnyvale, CA (Remote)

Duration:12+months

Minimum Qualifications

Design Verification Engineering Services

Testbench development System Verilog Universal Methodology (UVM), Python, and C tests

Integration/development of C tests/Application Programming Interface (APIs) and software build flow

Integration of UVM testbenches

Test development and debug, including without limitation tests for functionality, power, performance, error, and connectivity, both for RTL and Gate Level Netlist Design Under Test, tests for functional and code coverage improvements

Continuous integration and/or regression testing setup and debug for simulation at both RTL and Gate Level Netlist

Unified Power Format (UPF) power aware simulation/emulation

XProp simulation/regression TestBench creation and maintenance

Coverage collection and closure

Documentation of tests, testbench, use-cases, exclusions, and status


Desired Skills and Experience
Python, UVM, API, Testing

Education

Any Graduate