Full Chip LVS lead

Responsibilities:

LVS Verification Planning: Develop and execute comprehensive LVS verification plans for full chip designs to ensure layout accuracy and compliance with design specifications
Team Leadership: Lead and manage a team of LVS verification engineers responsible for performing LVS checks and resolving discrepancies in layout and schematic representations
Tool Selection and Setup: Evaluate, select, and set up LVS verification tools and flows, such as Cadence Assura, Mentor Calibre, Synopsys IC Validator, etc., for efficient and accurate verification
LVS Debugging: Oversee and participate in debugging LVS violations, identifying root causes, and collaborating with design teams to resolve layout and schematic discrepancies
Collaboration: Work closely with physical design teams, circuit designers, and other stakeholders to understand design intent, resolve LVS issues, and ensure layout correctness
Methodology Development: Develop and implement best practices, methodologies, and automation scripts for streamlining LVS verification processes and improving productivity
Documentation: Maintain documentation related to LVS verification plans, results, debug reports, and issues encountered during verification activities

Qualifications:

Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field
Experience: Several years of experience in LVS verification for complex full chip designs, including experience in a lead or senior role
LVS Tools: Proficiency in using industry-standard LVS verification tools such as Cadence Assura, Mentor Calibre, Synopsys IC Validator, etc., and familiarity with LVS verification methodologies
Scripting and Automation: Strong scripting skills in languages such as Tcl, Perl, or Python for developing automation scripts to enhance LVS verification efficiency and coverage
Layout and Schematic Understanding: In-depth understanding of layout design principles, schematic representations, and LVS verification methodologies to ensure accurate verification results
Debugging Skills: Excellent debugging and problem-solving skills, with the ability to analyze complex LVS violations and collaborate with design teams to resolve issues
Communication and Leadership: Strong communication, teamwork, and leadership skills to lead LVS verification projects, collaborate with cross-functional teams, and mentor junior engineers