Hardware Design Engineer 4

Job Description

Role: Hardware Design Engineer 4 -- 141148-1
Location: San Francisco, CA (Hybrid)
Duration: Contract

Top 3 Hard Skills Required + Years of Experience
• Proficient in using C/C++ (5+YOE)
• Systemverilog (5+ YOE)
• UVM experience required (5+ YOE) - VMM/OVM is a plus

Summary:
The main function of the Hardware Design Engineer is to be a part of the test-plan generation process, creating, testing, and implementing various verification plans.

Job Responsibilities:
• Define, document, and implement a UVM verification environment including agents and scoreboards
• Write test plans and implement them by developing tests, test generators, test benches, checkers, coverage, and other verification collateral
• Run tests on RTL and Gate Level Netlists, debug failures to root cause, and recommend fixes
• Support post-silicon verification activities of the products working with design and product teams

Skills:
• Proficient in using C/C++, Systemverilog and VMM/OVM/UVM
• Experience in pre and post silicon verification test flow and automated test benches
• Effective communication, collaboration, and teamwork skills