Physical Design (STA) Engineer

Roles & Responisbilities
 

Working with the Systems and Application team to drive timing closure-friendly SoC architecture and IO interfaces/IO pin

Streamlining the timing signoff criteria, timing analysis methodologies and flows (critical path spice simulation, etc.), and developing/enhancing auto ECO generation scripts for timing closure

Analyze and incorporate advance timing signoff flows (SSTA, LOCV Based STA, IR Drop aware STA) into SoC timing signoff flow

Enhance the existing entire timing flow from frontend (pre-layout) to backend (post-layout) at both chip level and block level

Ensure quality adherence during all stages of the project life cycle. Drive thorough analysis of existing processes and recommend and implement the process improvements to ensure 'Zero Defect' chips

Active participation in post-silicon validation, correlation, and test activities using in-house test and validation lab

Effectively lead highly energetic and intellectual team members through coaching and mentoring, provide technical direction for career planning, engage them on project issues, and manage change

Key Skills
Self-starter with 2-10 years of experience on SOC/Chip level/IP Timing closure and Signoff of high-speed complex design with multiple clocks and power domains with minimal supervision

Expertise in developing and owning full chip Timing Constraints for complex, multi-clock, multi-voltage SoCs. Exposure to Primetime (Synopsys is a must)

Expertise in the protocol of Industry standard IO interfaces (e.g., DDR2, SDR, LPDDR, Flash, SPIs, USBHS, USBFS, JTAG, Display, etc)

Experience in analyzing failure in Functional and Test Gate-level simulations with back annotated data and interacting with the Verification and DFT team in this respect

Expertise in running STA analysis and achieving timing closure on multiple high-performance and low-power designs

Experience in developing and supporting fully automated STA scripts/flows