Pre-Silicon Validation Engineer

Job Description: Pre-Silicon Validation Engineer

Location: Mountain View, CA

Hybrid work model (at least 2-3 days/week at Client site)

Type: Flexible for C2C (Corp to Corp) and W2

Preferred Qualification

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• B.Tech/M.Tech in Electronics Engg, Electrical Engg or Computer Science

• 10+ yrs experience in Pre-Silicon validation/Post Silicon validation

• Experience in using Emulation platform and FPGA prototyping platform

• Strong experience in C coding at Bare Metal/Firmware level

• Experience on Test plan development and Test infra development.

• Good understanding of CPU architecture (ARM/Client/MIPS, etc..)

• Working experience in Design protocol such as PCIe, AXI, USB, Gigabit Ethernet, MIPI, etc

• Working experience in low-speed protocols such as SPI, I2C, UART, Mixed signal IPs.

• Exposure to WiFi & Bluetooth protocols.

• Very good experience in Debugging code at the bare metal/Firmware level

• Usage of Measurement instruments like Oscilloscope, Logic Analyser, Current analyser, etc..

• Exposure to UVM methodology

Role

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• C coding for various IPs within the CPU

• Prepare validation plan and test code

• Prepare Functional code on Emulation and target the same for Post Silicon validation

• Cross communicates with various design teams & IP vendors

• Mentor & Co-ordinate with the team for task completion

• POC for any communication with the Vendor.

C coding for various IPs within the CPU

Prepare validation plan and test code

Prepare Functional code on Emulation and target the same for Post Silicon validation

Working experience in Design protocol such as PCIe, AXI, USB, Gigabit Ethernet, MIPI, etc

Working experience in low-speed protocols such as SPI, I2C, UART, Mixed signal IPs.

Knowledge of CPU architecture (ARM/Client/MIPS, etc..)

Skills:

Jasper (Priority:1)

Palladium (Priority: 1)

Python (Priority:3)

TCL or Perl (Priority: 3)