Product Owner / Senior Consultant

Knowledge required in the areas like- 
Develop detailed circuit specifications for mixed-signal circuits.
Design circuit architectures and transistor-level topologies to meet performance requirements.
Provide guidance for physical implementation (layout) of high-speed circuits.
Optimize circuits via simulation (using Cadence EDA tools) across various process and operating conditions.
Create cell/libraries models to be used for high level integrated functional and timing verification.
Integrate circuit elements into large analog/mixed-signal ASICs.
Participate in the characterization and testing of ASICs.
Help build test chip and validate. 
Have good understanding of PDK and various components within PDK.

Basic Qualifications & Skills 
Involved in all phases of multiple IC developments, from specification to product introduction.
Thorough knowledge of high-frequency, broad-band Analog Mixed-Signal IC design, covering both electrical and physical aspects.
Expertise in chip top-level logic and physical design, specializing in timing-aware logical partitioning, floor planning, and fast timing closure for mixed-signal chips.
Proficient in analog and mixed-signal modeling and verification for complex ICs, emphasizing functional and timing models as well as physical abstraction generation.
Solid understanding of Cadence RTL/STA/SDF gate-level verification flows.
Experience with standard and custom cell/IP cell library build, characterization, quality assurance, and release processes.
Collaborated extensively with EDA vendors to enhance tools and design flows, including Hard IP integration methodology.
Skilled in IC characterization at high frequency circuits, using tools such as high-speed sampling oscilloscopes, spectrum analyzers, VNAs, and signal sources.
Desired experience in CMOS FinFET (16nm or lower) design.
Verilog or Verilog-A modeling proficiency is a plus.