Senior Analog Layout Engineer

Job Description

Please find the JD below

Analog Layout Engineer / Senior Engineer Experience: 5- 8 Years Job Description:

• Layout in advanced CMOS technologies including floorplan, placement, routing, DRC, LVS etc.
• Should have worked on 5nm, 7nm, 14nm etc. technology nodes on various analog mixed signal blocks such as PLL, Band gap, ADC, DAC, SERDES, IO etc.
• Should be well versed with tools such as Virtuoso/ XL/ GXL, IC12.1, and Calibre etc.
• Exposure to automated place and route tools such as ICC, SOC Encounter etc. would be added advantage.
• Required to work with circuit designers to meet design specifications.
• Requires excellent teamwork, good communication and strong problem solving skills.
• Ability to collaborate with others across groups in a direct and productive manner with unquestionable integrity.
• Strong analytical ability, problem solving, and communication skills.

• Ability to work independently and at various levels of abstraction.
• Experience in CMOS Analog and mixed-signal layout designs of PLL, SerDes Phy, ADC, DAC, Oscillators and LDO’s in process nodes 28nm and below.
• Knowledge of basic circuits, matching constraints, Design-driven constraints expected according to experience level.
• Standard Analog layout techniques and good understanding of physical, electrical aspects of layout.
• Good understanding of reliability physics including EM, ESD, crosstalk, shielding, Latchup and deep sub-micron challenges.
• Experience in IO Ring and Testchip is a plus.
• Expertise in working on FinFet layouts.
• Hands on experience with Virtuoso(L/XL/GXL), Calibre, StarRC, Totem tools and familiarity in various physical verification checks DRC, LVS, DFM, ERC, EM, IR etc.