Senior Design Engineer

Responsibilities:

As Senior Design Engineer, you will work on developing memory Fast Cache instances for our next generation Arm Cores achieving outstanding PPA.

Required Skills and Experience :

We Prefer graduate or postgraduate from a university or Engineering School, in Electronic Engineering Degree.

• You must have 5+ years of experience in SRAM/memory designs, margin analysis, characterization and verification
• Expected to understand FE (Front end) models and Verilog
• High speed/low power CMOS circuit design, clocking schemes, Static, dynamic and complex logic circuits.
• Understanding of Power versus Performance versus Area trade-offs in typical CMOS design.
• Expected to have good interpersonal skills.

“Nice To Have” Skills and Experience :

• Basic scripting languages, e.g. Perl/TCL/Python.
• Proven experience of working on Cadence or Synopsys flows.
• Experience with Circuit Simulation and Optimization of standard cells.
• Experience in silicon validation and debug