Senior Design Verification Engineer

Position: Senior Design Verification Engineer
Location: Remote Any Where in USA
Experience: 10 to 15 Years
Duration: Contract on C2c/Full time 

Skills: System Verilog AND TEST AND UVM AND Verification AND Debug 

What you’ll be doing: 

• At-least 10+ years of experience in System Verilog HVL and C++/C 
• At-least 10+ year of experience in UVM. 
• Experience in complete verification cycle which includes development of test plan, BFM/Driver/Monitor/Scoreboard component development and integration in test bench, stress/corner testing, failure debug, gate level simulations, assertions, and coverage closure. 
• Proficient in SVTB/UVM, C++ test bench. 
• Understand DSP is a plus. 
• Subversion for Repository and Bugzilla is also a Plus. 
• Proficient in debug and assertions coding.
• Verification closure with team. 
• Make/Perl/Python / any script.
• Any protocol experience is fine. 
• Ensure customer satisfaction. 
• Reporting to customer on daily or weekly progress effectively.