Senior Engineer - Memory Design Validation.

Senior Engineer - Memory Design Validation.
Location: Bloomington, MN. 
Experience Required: 7+ Years.
Skills/Tools Required: SPCIE (HSPICE & PSPICE), Spectre, Calibre, Synopsys’ NanoSim and Cadence’s UltraSim and /or Similar tools. 
Notice Period: Immediate to 15 days. 
Work Authorizations: W2, 1099, H1B, H4 EAD and C2C. 
Job Description:
l Lead and contribute to the validation of custom memory designs and compilers.
l Verify functionality, identify design issues, and help fix them.
l Analyze signal integrity, find design weaknesses, and suggest solutions.
l Run transistor-level simulations to check for power-up or lock-up issues and resolve them.
l Perform EM/IR analysis to assess timing and internal margins.
l Validate timing and internal margins through transistor-level simulations, identify gaps, and resolve them.
l Conduct validation checks to ensure accurate timing and power models.
l Develop scripts to automate verification processes and data analysis.
l Support silicon debugging and correlate results with SPICE models.
l Collaborate with memory design leads, modeling leads, and managers to define and execute the validation plan.