Senior RTL Design Engineer

About the job

Position Overview:

Seeking an experienced ASIC RTL Design Engineer with at least 4 years of industry experience to join our team. As an ASIC RTL Design Engineer, you will be responsible for the design and implementation of complex digital circuits at the Register Transfer Level (RTL) for ASIC (Application-Specific Integrated Circuit) projects. Your expertise in RTL design, verification, and implementation will be crucial in delivering high-quality ASIC designs.

Responsibilities:

• RTL Design: Create and optimize RTL designs using industry-standard hardware description languages (HDLs) such as Verilog or VHDL. Ensure designs meet specifications, performance goals, and design constraints.
• Architecture and Microarchitecture: Contribute to the architectural and microarchitectural definition of ASIC projects. Collaborate with cross-functional teams including system architects, logic designers, and verification engineers to ensure cohesive design implementation.
• Verification Planning and Execution: Develop comprehensive test plans and perform RTL verification activities such as simulation, formal verification, and linting. Identify and resolve design issues and bugs, ensuring functional correctness of the design.
• Synthesis and Timing Closure: Work closely with the Physical Design team to guide the synthesis process and achieve timing closure. Optimize the design for area, power, and performance while meeting the required timing constraints.
• Design Documentation: Create and maintain design documentation, including specifications, design constraints, and integration guidelines. Contribute to design reviews and provide clear and concise design documentation for cross-functional teams.
• Collaboration and Communication: Collaborate effectively with cross-functional teams, including architects, designers, verification engineers, and physical design engineers. Communicate design requirements, progress, and issues clearly and timely.
• Emerging Technologies: Stay updated with the latest industry trends, tools, and methodologies related to ASIC design. Evaluate and propose new design techniques and methodologies to improve productivity and design quality.

Qualifications:

• Education: Bachelor's or Master's degree in Electrical or Computer Engineering, or a related field.
• Experience: At least 4 years of industry experience in ASIC RTL design and verification.
• RTL Design Languages: Proficiency in Verilog or VHDL for RTL design.
• ASIC Design Flow: Strong understanding of the ASIC design flow, including RTL design, verification, synthesis, and timing closure.
• Verification Methodologies: Experience with simulation-based verification, knowledge of formal verification techniques, and familiarity with verification languages (e.g., SystemVerilog, UVM) is a plus.
• EDA Tools: Familiarity with industry-standard EDA tools for synthesis, simulation, and timing analysis. Experience with FPGA prototyping is a plus.
• Scripting and Programming: Proficiency in scripting languages (e.g., Python, Tcl) and programming languages (e.g., C, C++) for design automation and modeling tasks.
• Problem-Solving Skills: Strong analytical and problem-solving skills to identify and debug design issues effectively.
• Communication and Teamwork: Excellent communication skills and the ability to work collaboratively in a team-oriented environment.
• Adaptability: Ability to adapt quickly to changing project requirements and prioritize tasks effectively.