Senior / Staff DFT Engineer

Job Description:

Arm’s Solutions group DFT team implements DFT for test-chips and hard-macros to prove Arm's soft IP power, performance, area, and functionality within the context of a SoC using the latest DFT techniques and process technologies. We closely collaborate with RTL, Verification, Physical Implementation, and Test engineering teams throughout the life cycle of a project, from an early investigation stage all the way through tape-out and silicon test/characterization on ATE.

Responsibilities:

Architect, Implement, and validate innovative DFT techniques on test-chips and hard-macros. Insert DFT logic into SoC-style designs at the RTL level and at the Synthesis gate level, validate all features, and generate ATE-targeted test patterns to be run on silicon. Work closely with front-end design and verification teams on DFT RTL level insertion, back-end synthesis, place-and-route, and static-timing-analysis teams on DFT gate level insertion and timing closure, and Test and Debug teams on silicon characterization and validation.

Required Skills and Experience:

• This role is for a Senior DFT Engineer with 5 + years of proven experience in Design for Test
• Experience coding in Verilog RTL, and scripting language like TCL, and/or Perl
• Proficient in Unix/Linux environments
• Core DFT skills considered crucial for this position should include some of the following: Scan compression and insertion, Memory BIST, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate-level verification, silicon debug
• Experience with Siemens, Cadence, and/or Synopsys DFT and simulation tools

“Nice To Have” Skills and Experience:

• Familiarity with IEEE 1149, 1500, 1687
• Familiarity with Synthesis and Static Timing Analysis
• Working knowledge of Siemens DFT tools
• Ability to work both collaboratively on a team and independently.
• Innovative and a passion for progress
• Hard-working and excellent time management skills with an ability to multi-task