SOC Design Verification Engineer

Job Description:

• Execute SoC verification tasks and work closely with team members to review and understand the relevant functional and safety-related requirements
• Work and align with different stakeholders to identify verification plans and define SOC verification strategies
• Execute the verification plan by developing C/C++ test cases and System Verilog /UVM testbench components and by integrating 3rd party VIPcomponents

Job Requirements:

• Masters/Bachelors in Electrical Engineering or Computer Science with more than 5 years of relevant work experience
• Understand the usage of tools like Xcelium, Spectre(X) and Simvision
• Strong foundational knowledge of digital/mixed-signal design & verification
• Knowledge and hands-on experience of System Verilog and UVM
• Exposure to version-controlling (eg, Git/Bitbucket, ClearCase, CVS, SVN) and bug management schemes
• Self-motivated, flexible and with strong interpersonal skills
• Good communication with interpersonal skills and is a good team player who is able to work well with both internal and external partners