UVM Development Engineer (Verification Expert)

UVM Development Engineer (Verification Expert)

Madrid,Spain

Permanent

Skills

Verification

Simulation

ABV

Debugging

UVM

Position: UVM Development Engineer (Verification Expert)

Location: Spain Madrid

Overview:

We are seeking an experienced UVM (Universal Verification Methodology) Development Engineer with

expertise in simulation tools like Cadence Xcelium (or similar), to join our verification team. The ideal

candidate will have a strong background in creating complex verification environments using UVM and

driving the verification of digital designs through simulation. This role is critical in ensuring the

functionality, performance, and reliability of ASIC/SoC and FPGA designs in cutting-edge projects.

Key Responsibilities:

1. UVM Testbench Development:

o Develop UVM-based testbenches to verify digital designs (ASICs, SoCs, or FPGAs) at the

block, subsystem, and system levels.

o Architect, design, and implement reusable verification components such as drivers,

monitors, scoreboards, and sequences.

o Create constrained-random test environments, functional coverage models, and

assertions to ensure comprehensive verification.

2. Simulation and Debugging:

o Use simulation tools such as Cadence Xcelium, Mentor Graphics Questa, Synopsys VCS,

or similar for running simulations and debugging complex designs.

o Analyze waveforms, logs, and results to pinpoint issues and resolve design or verification-

related bugs.

o Conduct regression testing, performance analysis, and ensure test coverage goals are met.

o Implement code and functional coverage, track metrics, and improve coverage closure.

3. Verification Planning and Execution:

o Develop detailed verification plans based on design specifications, functional

requirements, and target coverage metrics.

o Collaborate with design teams to understand the design architecture and define

verification strategies.

o Execute test cases for various configurations and modes of the design, ensuring

adherence to verification goals and milestones.

4. UVM Methodology Expertise:

o Ensure the use of best practices for UVM development, including adherence to coding

standards, object-oriented programming principles, and modularity.

o Optimize UVM testbench components for performance, reusability, and scalability.

o Mentor junior verification engineers on UVM methodology and best practices, providing

guidance on code reviews, debugging, and problem-solving.

5. Automation and Scripting:

o Develop automation scripts for simulation, regression runs, and reporting using scripting

languages such as Python, Perl, or Tcl.

o Implement makefiles, run scripts, and automation flows to streamline the verification

process and maximize efficiency.

6. Assertion-Based Verification (ABV):

o Leverage assertion-based verification techniques to capture critical design behaviors and

ensure proper functionality.

o Work with SystemVerilog assertions (SVA) and other formal verification techniques to

complement UVM-based verification.

7. Collaborative Development:

o Work closely with RTL designers, architects, and systems engineers to understand design

intent, review test plans, and resolve issues identified during verification.

o Contribute to code reviews, design reviews, and verification reviews to ensure the highest

level of quality in the verification process.

o Collaborate with cross-functional teams to ensure test environments are aligned with

overall project goals and timelines.

8. Documentation and Reporting:

o Document verification environment architecture, test plans, coverage metrics, and results

for internal and external stakeholders.

o Provide regular status updates, coverage reports, and detailed bug tracking to the project

team and management.

o Ensure version control of verification environments and track changes using Git, SVN, or

other version control systems.

Required Qualifications:

• Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a

related field.

• Experience:

o 10+ years of experience in UVM-based verification for digital IC/ASIC/SoC designs.

o Hands-on experience with simulation tools like Cadence Xcelium, Mentor Graphics

Questa, Synopsys VCS, or similar.

o Proficiency in SystemVerilog for verification, including the development of complex UVM

components and test environments.

o Experience with writing SystemVerilog Assertions (SVA) and using assertion-based

verification.

o Proven ability to create, maintain, and execute regression test suites for large-scale digital

designs.

Preferred Qualifications:

• Familiarity with formal verification methodologies and tools such as JasperGold.

• Knowledge of functional coverage techniques and strategies to ensure high-quality verification.

• Experience with Python, Perl, or Tcl scripting for automation of verification tasks.

• Familiarity with industry-standard interfaces such as AXI, PCIe, Ethernet, or DDR.

• Experience in low-power verification techniques, using tools like UPF/CPF.

• Knowledge of digital design concepts, such as RTL design, synthesis, and timing closure, to better

understand verification needs.

• Experience with multi-core or multi-processor verification.

Personal Attributes:

• Strong problem-solving skills and the ability to debug complex designs and test environments.

• Excellent communication skills, both written and verbal, for clear reporting and collaboration.

• Ability to work independently and in a team, with a proactive approach to resolving issues.

• Meticulous attention to detail and a commitment to delivering high-quality verification results.

Position: RTL Development Engineer (FPGA Expert)

Location: Madrid, Spain

Overview:

We are seeking an experienced RTL (Register Transfer Level) Development Engineer with expertise in FPGA

design and extensive knowledge of Xilinx/AMD tools, including Vivado. The successful candidate will play

a critical role in the design, development, verification, and implementation of FPGA-based solutions for

complex systems. This role requires a deep understanding of FPGA architecture, RTL design, simulation,

and synthesis, as well as proficiency in Vivado for hardware design, debugging, and verification.

Key Responsibilities:

1. RTL Design and Implementation:

o Design, develop, and optimize RTL code in VHDL/Verilog/SystemVerilog for FPGA-based

systems.

o Develop efficient, modular, and reusable RTL architectures for high-performance, low-

power, and scalable systems.

o Implement complex algorithms and digital signal processing (DSP) blocks for FPGA

targets.

o Perform RTL coding for custom IP cores and integration of third-party IP cores as per

project requirements.

2. FPGA Synthesis and Place-and-Route:

o Utilize Xilinx Vivado for synthesis, timing closure, and place-and-route of FPGA designs.

o Optimize FPGA resource utilization, timing, power, and area to meet design constraints

and specifications.

o Perform static timing analysis (STA) and ensure designs meet timing closure across all

operating conditions.

3. Verification and Debugging:

o Create testbenches and verify RTL designs using simulation tools such as ModelSim,

Questa, or Xilinx XSim.

o Perform pre-silicon verification, including functional and timing verification at RTL and

gate-level.

o Debug designs using simulation, logic analyzers, and in-circuit testing tools such as Vivado

ILA (Integrated Logic Analyzer) and Chipscope.

4. Vivado Toolchain Expertise:

o Utilize Vivado’s IP integrator to build complex FPGA systems using standard and custom

IPs.

o Work with Vivado HLS (High-Level Synthesis) to convert high-level algorithms (C/C++) into

RTL for FPGAs.

o Develop scripts for automation using TCL and other scripting languages within the Vivado

environment.

o Use Vivado’s bitstream generation and device programming tools to configure FPGAs.

5. System-Level Design:

o Design FPGA-based systems that integrate with microprocessors, DSPs, or custom

hardware.

o Work on SoC platforms such as Zynq/Zynq UltraScale+ by leveraging Xilinx tools to create

hardware-software co-designs.

o Collaborate with firmware, software, and hardware teams to integrate FPGAs into larger

systems and platforms.

6. Documentation and Compliance:

o Create and maintain detailed documentation, including design specifications, block

diagrams, and verification plans.

o Ensure designs are compliant with industry standards and specific project requirements.

o Work with teams on version control and design management using tools like Git.

7. Collaboration and Leadership:

o Provide technical guidance and mentorship to junior FPGA engineers.

o Work closely with cross-functional teams, including hardware, software, and product

engineering teams.

o Communicate effectively with stakeholders to discuss project progress, challenges, and

technical decisions.

Required Qualifications:

• Education: Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, or a

related field.

• Experience:

o 10+ years of hands-on experience in RTL design for FPGAs, including Xilinx/AMD devices.

o Extensive experience with Xilinx Vivado Design Suite, including synthesis, simulation, and

debugging.

o Solid understanding of FPGA architecture, timing analysis, and clock domain crossing

(CDC) techniques.

o Expertise in VHDL/Verilog/SystemVerilog coding for RTL design.

o Experience with FPGA verification methodologies (simulation, constrained random testing,

etc.).

Preferred Qualifications:

• Experience with Xilinx Zynq SoC (including Zynq UltraScale+) for hardware-software integration.

• Proficiency in Vivado HLS (High-Level Synthesis) and familiarity with C/C++ algorithm conversion

into hardware.

• Familiarity with industry standards such as AXI, PCIe, Ethernet, or other high-speed interfaces.

• Knowledge of FPGA design for signal processing, communication systems, or AI/ML accelerators.

• Familiarity with TCL scripting and automation in Vivado.

• Experience with embedded system design and development.

Personal Attributes:

• Strong problem-solving skills and the ability to troubleshoot complex digital designs.

• Excellent communication skills, both written and verbal.

• Ability to work in a team and independently with minimal supervision.

• Strong attention to detail and ability to document designs and processes thoroughly.